URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [src/] - Rev 57

Rev	Log message	Author	Age	Path
57	ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words	julius	5297d 06h	/openrisc/trunk/orpsocv2/bench/sysc/src/
53	Fixed incorrect commandline option for ORPSoC and main makefile setting	julius	5336d 06h	/openrisc/trunk/orpsocv2/bench/sysc/src/
52	ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation	julius	5337d 02h	/openrisc/trunk/orpsocv2/bench/sysc/src/
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5351d 04h	/openrisc/trunk/orpsocv2/bench/sysc/src/
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5369d 22h	/openrisc/trunk/orpsocv2/bench/sysc/src/
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5421d 09h	/openrisc/trunk/orpsocv2/bench/sysc/src/
42	Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model	julius	5461d 03h	/openrisc/trunk/orpsocv2/bench/sysc/src/
6	Checking in ORPSoCv2	julius	5483d 21h	/openrisc/trunk/orpsocv2/bench/sysc/src/