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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] - Rev 351

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Rev Log message Author Age Path
351 OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO julius 5022d 21h /openrisc/trunk/orpsocv2/bench/verilog/
348 First stage of ORPSoCv2 update - more to come julius 5023d 01h /openrisc/trunk/orpsocv2/bench/verilog/
69 ORPSoC xilinx ml501 board update - added ethernet eupport and software test julius 5223d 11h /openrisc/trunk/orpsocv2/bench/verilog/
67 New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory julius 5226d 06h /openrisc/trunk/orpsocv2/bench/verilog/
65 ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix julius 5250d 10h /openrisc/trunk/orpsocv2/bench/verilog/
57 ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words julius 5310d 02h /openrisc/trunk/orpsocv2/bench/verilog/
55 Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk julius 5320d 18h /openrisc/trunk/orpsocv2/bench/verilog/
51 ORPSoCv2 updates: cycle accurate profiling, ELF loading julius 5364d 01h /openrisc/trunk/orpsocv2/bench/verilog/
49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 5382d 18h /openrisc/trunk/orpsocv2/bench/verilog/
46 debug interfaces now support byte and non-aligned accesses from gdb julius 5398d 06h /openrisc/trunk/orpsocv2/bench/verilog/
44 New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades julius 5434d 05h /openrisc/trunk/orpsocv2/bench/verilog/
40 Added GDB server to verilog simulation via VPI and make target to build and run this model julius 5478d 06h /openrisc/trunk/orpsocv2/bench/verilog/
6 Checking in ORPSoCv2 julius 5496d 17h /openrisc/trunk/orpsocv2/bench/verilog/

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