Rev |
Log message |
Author |
Age |
Path |
361 |
OPRSoCv2 - adding things left out in last check-in |
julius |
5076d 03h |
/openrisc/trunk/orpsocv2/bench/verilog/ |
360 |
First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken |
julius |
5076d 03h |
/openrisc/trunk/orpsocv2/bench/verilog/ |
354 |
Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut
* sw/support/crt0.S: Tick timer interrupt to increment variable
now in place instead of calling customisable
interrupt vector handler
Changed all system frequencies in design to 50MHz. |
julius |
5078d 03h |
/openrisc/trunk/orpsocv2/bench/verilog/ |
351 |
OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO |
julius |
5079d 03h |
/openrisc/trunk/orpsocv2/bench/verilog/ |
348 |
First stage of ORPSoCv2 update - more to come |
julius |
5079d 07h |
/openrisc/trunk/orpsocv2/bench/verilog/ |
69 |
ORPSoC xilinx ml501 board update - added ethernet eupport and software test |
julius |
5279d 18h |
/openrisc/trunk/orpsocv2/bench/verilog/ |
67 |
New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory |
julius |
5282d 12h |
/openrisc/trunk/orpsocv2/bench/verilog/ |
65 |
ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix |
julius |
5306d 16h |
/openrisc/trunk/orpsocv2/bench/verilog/ |
57 |
ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words |
julius |
5366d 08h |
/openrisc/trunk/orpsocv2/bench/verilog/ |
55 |
Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk |
julius |
5377d 01h |
/openrisc/trunk/orpsocv2/bench/verilog/ |
51 |
ORPSoCv2 updates: cycle accurate profiling, ELF loading |
julius |
5420d 07h |
/openrisc/trunk/orpsocv2/bench/verilog/ |
49 |
Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update |
julius |
5439d 01h |
/openrisc/trunk/orpsocv2/bench/verilog/ |
46 |
debug interfaces now support byte and non-aligned accesses from gdb |
julius |
5454d 12h |
/openrisc/trunk/orpsocv2/bench/verilog/ |
44 |
New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades |
julius |
5490d 11h |
/openrisc/trunk/orpsocv2/bench/verilog/ |
40 |
Added GDB server to verilog simulation via VPI and make target to build and run this model |
julius |
5534d 12h |
/openrisc/trunk/orpsocv2/bench/verilog/ |
6 |
Checking in ORPSoCv2 |
julius |
5552d 23h |
/openrisc/trunk/orpsocv2/bench/verilog/ |