URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] - Rev 50

Rev	Log message	Author	Age	Path
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5403d 15h	/openrisc/trunk/orpsocv2/bench/verilog/
46	debug interfaces now support byte and non-aligned accesses from gdb	julius	5419d 03h	/openrisc/trunk/orpsocv2/bench/verilog/
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5455d 02h	/openrisc/trunk/orpsocv2/bench/verilog/
40	Added GDB server to verilog simulation via VPI and make target to build and run this model	julius	5499d 02h	/openrisc/trunk/orpsocv2/bench/verilog/
6	Checking in ORPSoCv2	julius	5517d 14h	/openrisc/trunk/orpsocv2/bench/verilog/