URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] - Rev 53

Rev	Log message	Author	Age	Path
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5362d 00h	/openrisc/trunk/orpsocv2/bench/verilog/
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5380d 18h	/openrisc/trunk/orpsocv2/bench/verilog/
46	debug interfaces now support byte and non-aligned accesses from gdb	julius	5396d 06h	/openrisc/trunk/orpsocv2/bench/verilog/
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5432d 05h	/openrisc/trunk/orpsocv2/bench/verilog/
40	Added GDB server to verilog simulation via VPI and make target to build and run this model	julius	5476d 05h	/openrisc/trunk/orpsocv2/bench/verilog/
6	Checking in ORPSoCv2	julius	5494d 17h	/openrisc/trunk/orpsocv2/bench/verilog/