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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] - Rev 63

Rev	Log message	Author	Age	Path
57	ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words	julius	5294d 05h	/openrisc/trunk/orpsocv2/bench/verilog/
55	Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk	julius	5304d 21h	/openrisc/trunk/orpsocv2/bench/verilog/
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5348d 03h	/openrisc/trunk/orpsocv2/bench/verilog/
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5366d 21h	/openrisc/trunk/orpsocv2/bench/verilog/
46	debug interfaces now support byte and non-aligned accesses from gdb	julius	5382d 08h	/openrisc/trunk/orpsocv2/bench/verilog/
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5418d 08h	/openrisc/trunk/orpsocv2/bench/verilog/
40	Added GDB server to verilog simulation via VPI and make target to build and run this model	julius	5462d 08h	/openrisc/trunk/orpsocv2/bench/verilog/
6	Checking in ORPSoCv2	julius	5480d 20h	/openrisc/trunk/orpsocv2/bench/verilog/