URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] - Rev 66

Rev	Log message	Author	Age	Path
65	ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix	julius	5248d 17h	/openrisc/trunk/orpsocv2/bench/verilog/
57	ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words	julius	5308d 09h	/openrisc/trunk/orpsocv2/bench/verilog/
55	Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk	julius	5319d 02h	/openrisc/trunk/orpsocv2/bench/verilog/
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5362d 08h	/openrisc/trunk/orpsocv2/bench/verilog/
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5381d 02h	/openrisc/trunk/orpsocv2/bench/verilog/
46	debug interfaces now support byte and non-aligned accesses from gdb	julius	5396d 13h	/openrisc/trunk/orpsocv2/bench/verilog/
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5432d 12h	/openrisc/trunk/orpsocv2/bench/verilog/
40	Added GDB server to verilog simulation via VPI and make target to build and run this model	julius	5476d 13h	/openrisc/trunk/orpsocv2/bench/verilog/
6	Checking in ORPSoCv2	julius	5495d 00h	/openrisc/trunk/orpsocv2/bench/verilog/