URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] - Rev 56

Rev	Log message	Author	Age	Path
55	Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk	julius	5388d 07h	/openrisc/trunk/orpsocv2/bench/verilog/
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5431d 13h	/openrisc/trunk/orpsocv2/bench/verilog/
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5450d 07h	/openrisc/trunk/orpsocv2/bench/verilog/
46	debug interfaces now support byte and non-aligned accesses from gdb	julius	5465d 18h	/openrisc/trunk/orpsocv2/bench/verilog/
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5501d 17h	/openrisc/trunk/orpsocv2/bench/verilog/
40	Added GDB server to verilog simulation via VPI and make target to build and run this model	julius	5545d 18h	/openrisc/trunk/orpsocv2/bench/verilog/
6	Checking in ORPSoCv2	julius	5564d 06h	/openrisc/trunk/orpsocv2/bench/verilog/