URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [include/] - Rev 491

Rev	Log message	Author	Age	Path
485	ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501	julius	4857d 06h	/openrisc/trunk/orpsocv2/bench/verilog/include/
408	ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too.	julius	4950d 14h	/openrisc/trunk/orpsocv2/bench/verilog/include/
403	ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly.	julius	4951d 20h	/openrisc/trunk/orpsocv2/bench/verilog/include/