URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [vpi/] - Rev 597

Rev	Log message	Author	Age	Path
493	ORPSoC VPI JTAG interface, hopefully fix 64-bit machine compile issues.	julius	5013d 16h	/openrisc/trunk/orpsocv2/bench/verilog/vpi/
425	ORPSoC update: GDB servers in VPI and System C model updated to deal with packets gdb-7.2 sends. Documentation updated. Reference design tests can now be run in or1ksim (added rule to sim/bin/Makefile). or1200-except doesn't appear to work as illegal instruction error isn't causing jump to vector. Updated Or1200 tests to report test success value and then exit with value 0.	julius	5111d 02h	/openrisc/trunk/orpsocv2/bench/verilog/vpi/
397	ORPSoCv2: doc/ path added, with Texinfo documentation. Still a work in progress. VPI files updated. OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction. Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build.	julius	5128d 12h	/openrisc/trunk/orpsocv2/bench/verilog/vpi/
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5541d 05h	/openrisc/trunk/orpsocv2/bench/verilog/vpi/
46	debug interfaces now support byte and non-aligned accesses from gdb	julius	5556d 17h	/openrisc/trunk/orpsocv2/bench/verilog/vpi/
40	Added GDB server to verilog simulation via VPI and make target to build and run this model	julius	5636d 16h	/openrisc/trunk/orpsocv2/bench/verilog/vpi/