OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [backend/] - Rev 542

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
542 ORPSoC scripts cleanup. Now centralised.

Documentation updated for ml501's SPI programming, noting issues with ISE12.
julius 4917d 02h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/
449 ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.

Replace use of "clean-all" with "distclean" as make rule to clean things.
julius 5074d 03h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.
julius 5081d 06h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/
408 ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too. julius 5114d 21h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.