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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [rtl/] - Rev 499

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Rev Log message Author Age Path
499 ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup julius 4832d 19h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/
485 ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 julius 4866d 07h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.		 julius 4926d 01h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/
435 ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality.		 julius 4932d 17h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/
425 ORPSoC update:

GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.

Documentation updated.

Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.

Updated Or1200 tests to report test success value and then
exit with value 0.		 julius 4945d 17h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/
411 Improved ethmac testbench and software.

Renamed some OR1200 library functions to be more generic.

Fixed bug with versatile_mem_ctrl for Actel board.

Added ability to simulate gatelevel modules alongside RTL modules
in board build.		 julius 4958d 04h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/
409 ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it.
Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build.
Updated documentation.		 julius 4959d 04h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/
408 ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too. julius 4959d 16h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/

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