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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [rtl/] [verilog/] [include/] - Rev 544

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Rev Log message Author Age Path
544 ORPSoC ordb1a3pe1500 update - adding SD card controller. julius 4762d 05h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/
542 ORPSoC scripts cleanup. Now centralised.

Documentation updated for ml501's SPI programming, noting issues with ISE12.		 julius 4767d 19h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/
530 ORPSoC update

Ethernet MAC Wishbone interface fixes

Beginnings of software update.

ML501 backend script fixes for new ISE		 julius 4791d 05h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/
503 ORPSoC's or1200 defines fix to indicate we don't actually have I/DMMU invalidate registers. julius 4834d 16h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/
502 ORPSoC update - or1200, ethmac Xilinx fifos
or1200 in ORPSoC has carry bit, overflow bit, and range exception added and tested. New software tests in ORPSoC library. Ml501 build had ethmac fifos added, and or1200_defines updated to use these new or1200 features by default		 julius 4836d 20h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/
499 ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup julius 4838d 17h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.		 julius 4932d 00h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/
435 ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality.		 julius 4938d 15h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/
409 ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it.
Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build.
Updated documentation.		 julius 4965d 02h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/
408 ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too. julius 4965d 14h /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/

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