URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] - Rev 417

Rev	Log message	Author	Age	Path
415	ORPSoC - ML501 update, working again. Documentation update including information on ML501 build OR1200 updates to do with instruction cache tag signal when invalidate instruction used. Added ability to define address to pass to SPI flash when booting. Added SPI sw test for board which allows inspection of data in a flash.	julius	5012d 22h	/openrisc/trunk/orpsocv2/boards/xilinx/
412	ORPSoC update - Rearranged Xilinx ML501, simulations working again.	julius	5016d 12h	/openrisc/trunk/orpsocv2/boards/xilinx/
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5071d 19h	/openrisc/trunk/orpsocv2/boards/xilinx/
71	ORPSoC board builds, adding readmes	julius	5271d 04h	/openrisc/trunk/orpsocv2/boards/xilinx/
69	ORPSoC xilinx ml501 board update - added ethernet eupport and software test	julius	5275d 10h	/openrisc/trunk/orpsocv2/boards/xilinx/
67	New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory	julius	5278d 04h	/openrisc/trunk/orpsocv2/boards/xilinx/