| Rev |
Log message |
Author |
Age |
Path |
| 496 |
ORPSoC ml501 updates - increased frequency, updated documentation |
julius |
4825d 20h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/ |
| 492 |
ORPSoC VPI interface for modelsim and documentation update |
julius |
4839d 20h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/ |
| 486 |
ORPSoC updates, mainly software, i2c driver |
julius |
4852d 18h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/ |
| 485 |
ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 |
julius |
4856d 22h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/ |
| 480 |
ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes. |
julius |
4874d 03h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/ |
| 479 |
ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. |
julius |
4875d 02h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/ |
| 478 |
ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups. |
julius |
4876d 18h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/ |
| 475 |
ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0. |
julius |
4877d 22h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/ |
| 468 |
ORPSoC update:
Added USER_ELF and USER_VMEM options to reference design simulation scripts.
Changed use of absolute BOARD_PATH variable to simply BOARD relative to board path
ML501's board.h bootrom default now boot from SPI |
julius |
4882d 23h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/ |
| 449 |
ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.
Replace use of "clean-all" with "distclean" as make rule to clean things. |
julius |
4909d 13h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/ |
| 439 |
ORPSoC update
Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST
Multiply/divide tests for to run on target.
Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.
Added ability to use ram_wb as internal memory on ML501 design.
Fixed ethernet MAC tests for ML501. |
julius |
4916d 16h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/ |
| 435 |
ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality. |
julius |
4923d 08h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/ |
| 426 |
ORPSoC update
Reverted back to previous OR1200 instruction cache.
(...which...)
Fixed or1200-except test failure on generic model.
ML501 build not passing or1200-except test. Tried disabling
burst on the bus (memory server doesn't support it yet) to
no avail. To be continued... |
julius |
4936d 07h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/ |
| 425 |
ORPSoC update:
GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.
Documentation updated.
Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.
Updated Or1200 tests to report test success value and then
exit with value 0. |
julius |
4936d 08h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/ |
| 415 |
ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash. |
julius |
4944d 17h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/ |
| 412 |
ORPSoC update - Rearranged Xilinx ML501, simulations working again. |
julius |
4948d 07h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/ |
| 360 |
First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken |
julius |
5003d 14h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/ |
| 71 |
ORPSoC board builds, adding readmes |
julius |
5202d 23h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/ |
| 69 |
ORPSoC xilinx ml501 board update - added ethernet eupport and software test |
julius |
5207d 04h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/ |
| 67 |
New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory |
julius |
5209d 23h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/ |
