| Rev |
Log message |
Author |
Age |
Path |
| 503 |
ORPSoC's or1200 defines fix to indicate we don't actually have I/DMMU invalidate registers. |
julius |
4995d 01h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/ |
| 502 |
ORPSoC update - or1200, ethmac Xilinx fifos
or1200 in ORPSoC has carry bit, overflow bit, and range exception added and tested. New software tests in ORPSoC library. Ml501 build had ethmac fifos added, and or1200_defines updated to use these new or1200 features by default |
julius |
4997d 05h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/ |
| 500 |
ORPSoC's System C UART model can now accept input from stdin during simulation to drive consoles etc
ML501 simulation makefile update to allow custom ELFs to be specified |
julius |
4998d 08h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/ |
| 499 |
ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup |
julius |
4999d 01h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/ |
| 496 |
ORPSoC ml501 updates - increased frequency, updated documentation |
julius |
5001d 11h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/ |
| 492 |
ORPSoC VPI interface for modelsim and documentation update |
julius |
5015d 12h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/ |
| 486 |
ORPSoC updates, mainly software, i2c driver |
julius |
5028d 09h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/ |
| 485 |
ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 |
julius |
5032d 14h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/ |
| 480 |
ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes. |
julius |
5049d 18h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/ |
| 479 |
ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. |
julius |
5050d 18h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/ |
| 478 |
ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups. |
julius |
5052d 09h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/ |
| 475 |
ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0. |
julius |
5053d 13h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/ |
| 468 |
ORPSoC update:
Added USER_ELF and USER_VMEM options to reference design simulation scripts.
Changed use of absolute BOARD_PATH variable to simply BOARD relative to board path
ML501's board.h bootrom default now boot from SPI |
julius |
5058d 14h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/ |
| 449 |
ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.
Replace use of "clean-all" with "distclean" as make rule to clean things. |
julius |
5085d 04h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/ |
| 439 |
ORPSoC update
Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST
Multiply/divide tests for to run on target.
Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.
Added ability to use ram_wb as internal memory on ML501 design.
Fixed ethernet MAC tests for ML501. |
julius |
5092d 08h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/ |
| 435 |
ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality. |
julius |
5098d 23h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/ |
| 426 |
ORPSoC update
Reverted back to previous OR1200 instruction cache.
(...which...)
Fixed or1200-except test failure on generic model.
ML501 build not passing or1200-except test. Tried disabling
burst on the bus (memory server doesn't support it yet) to
no avail. To be continued... |
julius |
5111d 22h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/ |
| 425 |
ORPSoC update:
GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.
Documentation updated.
Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.
Updated Or1200 tests to report test success value and then
exit with value 0. |
julius |
5112d 00h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/ |
| 415 |
ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash. |
julius |
5120d 08h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/ |
| 412 |
ORPSoC update - Rearranged Xilinx ML501, simulations working again. |
julius |
5123d 22h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/ |
