OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [backend/] - Rev 854

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
655 ORPSoC: add CFI flash controller to ml501, sw driver, tests, app, documentation julius 4609d 06h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/
638 orpsoc: xilinx: use XILINX env variable

instead of rely on custom environment variables,
use the XILINX variable and instruct the user how to
source the scripts that set it.

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>		 stekern 4663d 23h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/
560 ORPSoC update - update make scripts, XILINX_PATH setup changes.

Note - may require a change to XILINX_PATH on user systems.		 julius 4742d 04h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/
542 ORPSoC scripts cleanup. Now centralised.

Documentation updated for ml501's SPI programming, noting issues with ISE12.		 julius 4765d 07h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/
530 ORPSoC update

Ethernet MAC Wishbone interface fixes

Beginnings of software update.

ML501 backend script fixes for new ISE		 julius 4788d 17h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/
496 ORPSoC ml501 updates - increased frequency, updated documentation julius 4838d 15h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/
479 ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. julius 4887d 21h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/
478 ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups. julius 4889d 13h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/
449 ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.

Replace use of "clean-all" with "distclean" as make rule to clean things.		 julius 4922d 08h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/
415 ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash.		 julius 4957d 12h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.