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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [backend/] [par/] - Rev 542

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542 ORPSoC scripts cleanup. Now centralised.

Documentation updated for ml501's SPI programming, noting issues with ISE12.		 julius 4765d 20h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/
530 ORPSoC update

Ethernet MAC Wishbone interface fixes

Beginnings of software update.

ML501 backend script fixes for new ISE		 julius 4789d 06h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/
496 ORPSoC ml501 updates - increased frequency, updated documentation julius 4839d 03h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/
479 ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. julius 4888d 10h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/
478 ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups. julius 4890d 01h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/
449 ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.

Replace use of "clean-all" with "distclean" as make rule to clean things.		 julius 4922d 20h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/
415 ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash.		 julius 4958d 00h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/
69 ORPSoC xilinx ml501 board update - added ethernet eupport and software test julius 5220d 12h /par/
67 New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory julius 5223d 06h /par/

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