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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [backend/] [par/] - Rev 831

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Rev Log message Author Age Path
655 ORPSoC: add CFI flash controller to ml501, sw driver, tests, app, documentation julius 4773d 00h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/
638 orpsoc: xilinx: use XILINX env variable

instead of rely on custom environment variables,
use the XILINX variable and instruct the user how to
source the scripts that set it.

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>		 stekern 4827d 17h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/
560 ORPSoC update - update make scripts, XILINX_PATH setup changes.

Note - may require a change to XILINX_PATH on user systems.		 julius 4905d 22h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/
542 ORPSoC scripts cleanup. Now centralised.

Documentation updated for ml501's SPI programming, noting issues with ISE12.		 julius 4929d 01h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/
530 ORPSoC update

Ethernet MAC Wishbone interface fixes

Beginnings of software update.

ML501 backend script fixes for new ISE		 julius 4952d 11h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/
496 ORPSoC ml501 updates - increased frequency, updated documentation julius 5002d 09h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/
479 ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. julius 5051d 15h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/
478 ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups. julius 5053d 07h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/
449 ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.

Replace use of "clean-all" with "distclean" as make rule to clean things.		 julius 5086d 02h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/
415 ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash.		 julius 5121d 06h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/
69 ORPSoC xilinx ml501 board update - added ethernet eupport and software test julius 5383d 17h /par/
67 New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory julius 5386d 12h /par/

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