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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [backend/] [par/] - Rev 478

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Rev Log message Author Age Path
478 ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups. julius 4923d 18h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/
449 ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.

Replace use of "clean-all" with "distclean" as make rule to clean things.
julius 4956d 13h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/
415 ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash.
julius 4991d 17h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/
69 ORPSoC xilinx ml501 board update - added ethernet eupport and software test julius 5254d 04h /par/
67 New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory julius 5256d 23h /par/

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