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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [bench/] - Rev 475

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Rev	Log message	Author	Age	Path
439	ORPSoC update Ethernet MAC synthesis issues with Actel Synplify D-2009.12A Ethernet MAC FIFO synthesis issues with Xilinx XST Multiply/divide tests for to run on target. Added third interface to ram_wb module, changed reference design RAM to ram_wb wrapper. Updated verilog and system C monitor modules accordingly. Added ability to use ram_wb as internal memory on ML501 design. Fixed ethernet MAC tests for ML501.	julius	4931d 12h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/
415	ORPSoC - ML501 update, working again. Documentation update including information on ML501 build OR1200 updates to do with instruction cache tag signal when invalidate instruction used. Added ability to define address to pass to SPI flash when booting. Added SPI sw test for board which allows inspection of data in a flash.	julius	4959d 12h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/
412	ORPSoC update - Rearranged Xilinx ML501, simulations working again.	julius	4963d 02h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5018d 09h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/
69	ORPSoC xilinx ml501 board update - added ethernet eupport and software test	julius	5222d 00h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/
67	New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory	julius	5224d 18h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/

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