URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [bench/] [verilog/] - Rev 480

Rev	Log message	Author	Age	Path
480	ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes.	julius	4874d 06h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/
439	ORPSoC update Ethernet MAC synthesis issues with Actel Synplify D-2009.12A Ethernet MAC FIFO synthesis issues with Xilinx XST Multiply/divide tests for to run on target. Added third interface to ram_wb module, changed reference design RAM to ram_wb wrapper. Updated verilog and system C monitor modules accordingly. Added ability to use ram_wb as internal memory on ML501 design. Fixed ethernet MAC tests for ML501.	julius	4916d 20h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/
415	ORPSoC - ML501 update, working again. Documentation update including information on ML501 build OR1200 updates to do with instruction cache tag signal when invalidate instruction used. Added ability to define address to pass to SPI flash when booting. Added SPI sw test for board which allows inspection of data in a flash.	julius	4944d 20h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/
412	ORPSoC update - Rearranged Xilinx ML501, simulations working again.	julius	4948d 10h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5003d 18h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/