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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [bench/] [verilog/] [include/] - Rev 482

Rev	Log message	Author	Age	Path
482	ORPSoC updates - adding parity checking RTL, ethernet MAC FIFO buffer updates. Software changes.	julius	4923d 17h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/include/
480	ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes.	julius	4924d 19h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/include/
439	ORPSoC update Ethernet MAC synthesis issues with Actel Synplify D-2009.12A Ethernet MAC FIFO synthesis issues with Xilinx XST Multiply/divide tests for to run on target. Added third interface to ram_wb module, changed reference design RAM to ram_wb wrapper. Updated verilog and system C monitor modules accordingly. Added ability to use ram_wb as internal memory on ML501 design. Fixed ethernet MAC tests for ML501.	julius	4967d 09h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/include/
415	ORPSoC - ML501 update, working again. Documentation update including information on ML501 build OR1200 updates to do with instruction cache tag signal when invalidate instruction used. Added ability to define address to pass to SPI flash when booting. Added SPI sw test for board which allows inspection of data in a flash.	julius	4995d 09h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/include/
412	ORPSoC update - Rearranged Xilinx ML501, simulations working again.	julius	4998d 23h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/include/