| Rev |
Log message |
Author |
Age |
Path |
| 499 |
ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup |
julius |
4872d 15h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ |
| 496 |
ORPSoC ml501 updates - increased frequency, updated documentation |
julius |
4875d 01h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ |
| 485 |
ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 |
julius |
4906d 03h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ |
| 480 |
ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes. |
julius |
4923d 08h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ |
| 479 |
ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. |
julius |
4924d 07h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ |
| 478 |
ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups. |
julius |
4925d 23h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ |
| 439 |
ORPSoC update
Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST
Multiply/divide tests for to run on target.
Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.
Added ability to use ram_wb as internal memory on ML501 design.
Fixed ethernet MAC tests for ML501. |
julius |
4965d 22h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ |
| 435 |
ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality. |
julius |
4972d 13h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ |
| 426 |
ORPSoC update
Reverted back to previous OR1200 instruction cache.
(...which...)
Fixed or1200-except test failure on generic model.
ML501 build not passing or1200-except test. Tried disabling
burst on the bus (memory server doesn't support it yet) to
no avail. To be continued... |
julius |
4985d 12h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ |
| 415 |
ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash. |
julius |
4993d 22h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ |
| 412 |
ORPSoC update - Rearranged Xilinx ML501, simulations working again. |
julius |
4997d 12h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ |
| 69 |
ORPSoC xilinx ml501 board update - added ethernet eupport and software test |
julius |
5256d 10h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ |
| 67 |
New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory |
julius |
5259d 04h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ |
