| Rev |
Log message |
Author |
Age |
Path |
| 502 |
ORPSoC update - or1200, ethmac Xilinx fifos
or1200 in ORPSoC has carry bit, overflow bit, and range exception added and tested. New software tests in ORPSoC library. Ml501 build had ethmac fifos added, and or1200_defines updated to use these new or1200 features by default |
julius |
4986d 06h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/ |
| 499 |
ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup |
julius |
4988d 03h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/ |
| 496 |
ORPSoC ml501 updates - increased frequency, updated documentation |
julius |
4990d 13h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/ |
| 485 |
ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 |
julius |
5021d 16h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/ |
| 480 |
ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes. |
julius |
5038d 20h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/ |
| 479 |
ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. |
julius |
5039d 20h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/ |
| 478 |
ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups. |
julius |
5041d 11h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/ |
| 439 |
ORPSoC update
Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST
Multiply/divide tests for to run on target.
Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.
Added ability to use ram_wb as internal memory on ML501 design.
Fixed ethernet MAC tests for ML501. |
julius |
5081d 10h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/ |
| 435 |
ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality. |
julius |
5088d 01h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/ |
| 426 |
ORPSoC update
Reverted back to previous OR1200 instruction cache.
(...which...)
Fixed or1200-except test failure on generic model.
ML501 build not passing or1200-except test. Tried disabling
burst on the bus (memory server doesn't support it yet) to
no avail. To be continued... |
julius |
5101d 00h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/ |
| 415 |
ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash. |
julius |
5109d 10h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/ |
| 412 |
ORPSoC update - Rearranged Xilinx ML501, simulations working again. |
julius |
5113d 00h |
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/ |
