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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [rtl/] [verilog/] - Rev 439

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Rev Log message Author Age Path
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.		 julius 5090d 15h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/
435 ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality.		 julius 5097d 06h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/
426 ORPSoC update

Reverted back to previous OR1200 instruction cache.
(...which...)
Fixed or1200-except test failure on generic model.

ML501 build not passing or1200-except test. Tried disabling
burst on the bus (memory server doesn't support it yet) to
no avail. To be continued...		 julius 5110d 05h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/
415 ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash.		 julius 5118d 15h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/
412 ORPSoC update - Rearranged Xilinx ML501, simulations working again. julius 5122d 05h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/

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