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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [sim/] - Rev 530

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Rev Log message Author Age Path
500 ORPSoC's System C UART model can now accept input from stdin during simulation to drive consoles etc

ML501 simulation makefile update to allow custom ELFs to be specified		 julius 4823d 20h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/
492 ORPSoC VPI interface for modelsim and documentation update julius 4841d 00h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/
479 ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. julius 4876d 06h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/
475 ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0. julius 4879d 01h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/
468 ORPSoC update:
Added USER_ELF and USER_VMEM options to reference design simulation scripts.
Changed use of absolute BOARD_PATH variable to simply BOARD relative to board path
ML501's board.h bootrom default now boot from SPI		 julius 4884d 03h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/
449 ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.

Replace use of "clean-all" with "distclean" as make rule to clean things.		 julius 4910d 17h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/
425 ORPSoC update:

GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.

Documentation updated.

Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.

Updated Or1200 tests to report test success value and then
exit with value 0.		 julius 4937d 12h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/
415 ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash.		 julius 4945d 21h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/
412 ORPSoC update - Rearranged Xilinx ML501, simulations working again. julius 4949d 11h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/
71 ORPSoC board builds, adding readmes julius 5204d 03h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/
69 ORPSoC xilinx ml501 board update - added ethernet eupport and software test julius 5208d 08h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/
67 New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory julius 5211d 03h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/

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