URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [sw/] - Rev 435

Rev	Log message	Author	Age	Path
426	ORPSoC update Reverted back to previous OR1200 instruction cache. (...which...) Fixed or1200-except test failure on generic model. ML501 build not passing or1200-except test. Tried disabling burst on the bus (memory server doesn't support it yet) to no avail. To be continued...	julius	4936d 06h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/
415	ORPSoC - ML501 update, working again. Documentation update including information on ML501 build OR1200 updates to do with instruction cache tag signal when invalidate instruction used. Added ability to define address to pass to SPI flash when booting. Added SPI sw test for board which allows inspection of data in a flash.	julius	4944d 16h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/
412	ORPSoC update - Rearranged Xilinx ML501, simulations working again.	julius	4948d 06h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/
69	ORPSoC xilinx ml501 board update - added ethernet eupport and software test	julius	5207d 04h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/
67	New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory	julius	5209d 22h	/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/