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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [sw/] [board/] - Rev 866

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Rev Log message Author Age Path
655 ORPSoC: add CFI flash controller to ml501, sw driver, tests, app, documentation julius 4775d 18h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board/
496 ORPSoC ml501 updates - increased frequency, updated documentation julius 5005d 03h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board/
486 ORPSoC updates, mainly software, i2c driver julius 5032d 00h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board/
485 ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 julius 5036d 05h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board/
479 ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. julius 5054d 09h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board/
468 ORPSoC update:
Added USER_ELF and USER_VMEM options to reference design simulation scripts.
Changed use of absolute BOARD_PATH variable to simply BOARD relative to board path
ML501's board.h bootrom default now boot from SPI		 julius 5062d 06h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board/
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.		 julius 5095d 23h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board/
426 ORPSoC update

Reverted back to previous OR1200 instruction cache.
(...which...)
Fixed or1200-except test failure on generic model.

ML501 build not passing or1200-except test. Tried disabling
burst on the bus (memory server doesn't support it yet) to
no avail. To be continued...		 julius 5115d 14h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board/
415 ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash.		 julius 5124d 00h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board/
412 ORPSoC update - Rearranged Xilinx ML501, simulations working again. julius 5127d 14h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board/

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