OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [syn/] [xst/] [bin/] - Rev 629

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
542 ORPSoC scripts cleanup. Now centralised.

Documentation updated for ml501's SPI programming, noting issues with ISE12.
julius 4821d 19h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/xst/bin/
530 ORPSoC update

Ethernet MAC Wishbone interface fixes

Beginnings of software update.

ML501 backend script fixes for new ISE
julius 4845d 05h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/xst/bin/
468 ORPSoC update:
Added USER_ELF and USER_VMEM options to reference design simulation scripts.
Changed use of absolute BOARD_PATH variable to simply BOARD relative to board path
ML501's board.h bootrom default now boot from SPI
julius 4952d 05h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/xst/bin/
449 ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.

Replace use of "clean-all" with "distclean" as make rule to clean things.
julius 4978d 19h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/xst/bin/
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.
julius 4985d 23h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/xst/bin/
435 ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality.
julius 4992d 14h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/xst/bin/
415 ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash.
julius 5013d 23h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/xst/bin/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.