URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [doc/] - Rev 415

Rev	Log message	Author	Age	Path
415	ORPSoC - ML501 update, working again. Documentation update including information on ML501 build OR1200 updates to do with instruction cache tag signal when invalidate instruction used. Added ability to define address to pass to SPI flash when booting. Added SPI sw test for board which allows inspection of data in a flash.	julius	5109d 14h	/openrisc/trunk/orpsocv2/doc/
410	ORPSoC: Adding README in root explaining how to build documentation, and documentation fixup so it builds properly again.	julius	5114d 15h	/openrisc/trunk/orpsocv2/doc/
409	ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it. Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build. Updated documentation.	julius	5114d 15h	/openrisc/trunk/orpsocv2/doc/
408	ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too.	julius	5115d 04h	/openrisc/trunk/orpsocv2/doc/
397	ORPSoCv2: doc/ path added, with Texinfo documentation. Still a work in progress. VPI files updated. OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction. Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build.	julius	5118d 15h	/openrisc/trunk/orpsocv2/doc/