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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [doc/] - Rev 517

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Rev Log message Author Age Path
496 ORPSoC ml501 updates - increased frequency, updated documentation julius 4990d 08h /openrisc/trunk/orpsocv2/doc/
492 ORPSoC VPI interface for modelsim and documentation update julius 5004d 08h /openrisc/trunk/orpsocv2/doc/
485 ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 julius 5021d 10h /openrisc/trunk/orpsocv2/doc/
479 ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. julius 5039d 14h /openrisc/trunk/orpsocv2/doc/
468 ORPSoC update:
Added USER_ELF and USER_VMEM options to reference design simulation scripts.
Changed use of absolute BOARD_PATH variable to simply BOARD relative to board path
ML501's board.h bootrom default now boot from SPI
julius 5047d 11h /openrisc/trunk/orpsocv2/doc/
449 ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.

Replace use of "clean-all" with "distclean" as make rule to clean things.
julius 5074d 01h /openrisc/trunk/orpsocv2/doc/
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.
julius 5081d 04h /openrisc/trunk/orpsocv2/doc/
425 ORPSoC update:

GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.

Documentation updated.

Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.

Updated Or1200 tests to report test success value and then
exit with value 0.
julius 5100d 20h /openrisc/trunk/orpsocv2/doc/
417 ORPSoC re-adding doc automake files, this time not symlinks julius 5109d 04h /openrisc/trunk/orpsocv2/doc/
416 ORPSoC doc cleanup - removing symlinks from automake'd docs build path julius 5109d 04h /openrisc/trunk/orpsocv2/doc/
415 ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash.
julius 5109d 05h /openrisc/trunk/orpsocv2/doc/
410 ORPSoC: Adding README in root explaining how to build documentation, and
documentation fixup so it builds properly again.
julius 5114d 06h /openrisc/trunk/orpsocv2/doc/
409 ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it.
Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build.
Updated documentation.
julius 5114d 06h /openrisc/trunk/orpsocv2/doc/
408 ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too. julius 5114d 19h /openrisc/trunk/orpsocv2/doc/
397 ORPSoCv2:

doc/ path added, with Texinfo documentation. Still a work in progress.

VPI files updated.

OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.

Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build.
julius 5118d 06h /openrisc/trunk/orpsocv2/doc/

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