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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] - Rev 84

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Rev Log message Author Age Path
69 ORPSoC xilinx ml501 board update - added ethernet eupport and software test julius 5382d 17h /openrisc/trunk/orpsocv2/rtl/
67 New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory julius 5385d 12h /openrisc/trunk/orpsocv2/rtl/
65 ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix julius 5409d 16h /openrisc/trunk/orpsocv2/rtl/
63 Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. julius 5422d 08h /openrisc/trunk/orpsocv2/rtl/
58 ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up julius 5464d 04h /openrisc/trunk/orpsocv2/rtl/
57 ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words julius 5469d 08h /openrisc/trunk/orpsocv2/rtl/
55 Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk julius 5480d 00h /openrisc/trunk/orpsocv2/rtl/
54 wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist julius 5490d 07h /openrisc/trunk/orpsocv2/rtl/
51 ORPSoCv2 updates: cycle accurate profiling, ELF loading julius 5523d 06h /openrisc/trunk/orpsocv2/rtl/
49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 5542d 00h /openrisc/trunk/orpsocv2/rtl/
46 debug interfaces now support byte and non-aligned accesses from gdb julius 5557d 11h /openrisc/trunk/orpsocv2/rtl/
44 New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades julius 5593d 11h /openrisc/trunk/orpsocv2/rtl/
43 Couple of fixes to ORPSoC, new linux patch version in toolchain script julius 5617d 08h /openrisc/trunk/orpsocv2/rtl/
41 Update to or1k top julius 5636d 06h /openrisc/trunk/orpsocv2/rtl/
6 Checking in ORPSoCv2 julius 5655d 23h /openrisc/trunk/orpsocv2/rtl/

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