Rev |
Log message |
Author |
Age |
Path |
545 |
ORPSoC - revert unecessary i2c fix - driver oneliner was all that was needed. |
julius |
4851d 02h |
/openrisc/trunk/orpsocv2/rtl/ |
543 |
i2c_master_slave bug fix for slave, potentially holding SDA low when master wants to send stop. |
julius |
4851d 09h |
/openrisc/trunk/orpsocv2/rtl/ |
537 |
ORPSoC or1200 fix for l.rfe bug, and when multiply is disabled. |
julius |
4867d 20h |
/openrisc/trunk/orpsocv2/rtl/ |
536 |
ORPSoC - removing duplicate ethmac toplevel file. |
julius |
4871d 10h |
/openrisc/trunk/orpsocv2/rtl/ |
530 |
ORPSoC update
Ethernet MAC Wishbone interface fixes
Beginnings of software update.
ML501 backend script fixes for new ISE |
julius |
4880d 09h |
/openrisc/trunk/orpsocv2/rtl/ |
506 |
ORPSoC or1200 interrupt and syscall generation test |
julius |
4906d 03h |
/openrisc/trunk/orpsocv2/rtl/ |
505 |
OR1200 overflow detection fixup
SPIflash program update
or1200 driver library timer improvement |
julius |
4906d 04h |
/openrisc/trunk/orpsocv2/rtl/ |
504 |
ORPSoC ALU update with new comparison configuration option, software test for comparisons and register file comment cleanup |
julius |
4923d 00h |
/openrisc/trunk/orpsocv2/rtl/ |
503 |
ORPSoC's or1200 defines fix to indicate we don't actually have I/DMMU invalidate registers. |
julius |
4923d 20h |
/openrisc/trunk/orpsocv2/rtl/ |
502 |
ORPSoC update - or1200, ethmac Xilinx fifos
or1200 in ORPSoC has carry bit, overflow bit, and range exception added and tested. New software tests in ORPSoC library. Ml501 build had ethmac fifos added, and or1200_defines updated to use these new or1200 features by default |
julius |
4926d 00h |
/openrisc/trunk/orpsocv2/rtl/ |
501 |
ORPSoC or1200 mult/mac/divide unit serial arith bug fixed.
ORPSoC or1200 defines now use serial divide by default |
julius |
4927d 00h |
/openrisc/trunk/orpsocv2/rtl/ |
499 |
ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup |
julius |
4927d 20h |
/openrisc/trunk/orpsocv2/rtl/ |
485 |
ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 |
julius |
4961d 09h |
/openrisc/trunk/orpsocv2/rtl/ |
479 |
ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. |
julius |
4979d 13h |
/openrisc/trunk/orpsocv2/rtl/ |
478 |
ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups. |
julius |
4981d 04h |
/openrisc/trunk/orpsocv2/rtl/ |
477 |
ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each. |
julius |
4981d 13h |
/openrisc/trunk/orpsocv2/rtl/ |
476 |
ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more. |
julius |
4982d 06h |
/openrisc/trunk/orpsocv2/rtl/ |
462 |
ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.
RAM models updated. |
julius |
4989d 12h |
/openrisc/trunk/orpsocv2/rtl/ |
456 |
ORPSoCv2 or1200 - SPRs module format and comment update. Or1200 monitor Verilog now displays report and exit l.nops to stdout by default. |
julius |
5001d 04h |
/openrisc/trunk/orpsocv2/rtl/ |
439 |
ORPSoC update
Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST
Multiply/divide tests for to run on target.
Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.
Added ability to use ram_wb as internal memory on ML501 design.
Fixed ethernet MAC tests for ML501. |
julius |
5021d 03h |
/openrisc/trunk/orpsocv2/rtl/ |