Rev |
Log message |
Author |
Age |
Path |
363 |
ORPSoC's RTL code fixed to pass linting by Verilator.
ORPSoC's debug interface disabled for now in both RTL and System C top level.
Profiled building of cycle-accurate model now done correctly. |
julius |
5096d 02h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
362 |
ORPSoCv2 verilator building working again. Board build fixes to follow |
julius |
5097d 11h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
361 |
OPRSoCv2 - adding things left out in last check-in |
julius |
5097d 16h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
360 |
First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken |
julius |
5097d 16h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
358 |
OR1200's reset now configurable as active high or active low. Thanks to patch
from OpenCores contributor Kuoping.
Updated OR1200 in ORPSoCv2 and OR1200 project. |
julius |
5098d 01h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
356 |
Added new simple MAC test to ORPSoC test suite:
* orpsocv2/sw/or1200asm/or1200asm-mac.S: Added
Fixed MAC pipeline issue in OR1200
* or1200/rtl/verilog/or1200_mult_mac.v: Made mac_op valid only once per insn.
* orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v: ""
* orpsocv2/sw/dhry/dhry.c: Changed final output to be same as ORPmon version
* orpsocv2/sim/bin/Makefile: Added new MAC test to default tests |
julius |
5098d 10h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
353 |
OR1200 RTL and ORPSoCv2 update, fixing Verilator build capability.
* or1200/rtl/verilog/or1200_sprs.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_sprs.v: ""
* or1200/rtl/verilog/or1200_ctrl.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_ctrl.v: ""
* or1200/rtl/verilog/or1200_except.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_except.v: ""
* orpsocv2/rtl/verilog/components/wb_ram_b3/wb_ram_b3.v: Some
Verilator related Lint issues fixed.
ORPSoCv2: Removed bus arbiter snooping functions from OrpsocAccess and
updated RAM model hooks for new RAM.
* orpsocv2/bench/sysc/include/Or1200MonitorSC.h: Remove arbiter snooping
* orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp: ""
* orpsocv2/bench/sysc/include/OrpsocAccess.h: Remove arbiter snooping,
change include and classes for new RAM model.
* orpsocv2/bench/sysc/src/OrpsocAccess.cpp: ""
or_debug_proxy - fixing sleep and Windows make issues:
* or_debug_proxy/src/gdb.c: Removed all sleep - still to be fixed properly
* or_debug_proxy/Makefile: Remove VPI file when building on Cygwin (deprecated)
ORPmon play around, various changes to low level files. |
julius |
5099d 18h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
351 |
OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO |
julius |
5100d 16h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
350 |
Adding new OR1200 processor to ORPSoCv2 |
julius |
5100d 20h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
348 |
First stage of ORPSoCv2 update - more to come |
julius |
5100d 20h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
185 |
Adding single precision FPU to or1200, initial checkin, not fully tested yet |
julius |
5158d 19h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
69 |
ORPSoC xilinx ml501 board update - added ethernet eupport and software test |
julius |
5301d 07h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
67 |
New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory |
julius |
5304d 01h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
65 |
ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix |
julius |
5328d 05h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
63 |
Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. |
julius |
5340d 22h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
58 |
ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up |
julius |
5382d 17h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
57 |
ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words |
julius |
5387d 21h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
55 |
Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk |
julius |
5398d 14h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
54 |
wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist |
julius |
5408d 21h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
51 |
ORPSoCv2 updates: cycle accurate profiling, ELF loading |
julius |
5441d 20h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |