| Rev |
Log message |
Author |
Age |
Path |
| 570 |
Fix white space in ethmac headers |
olof |
4871d 22h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 547 |
ORPSoC dbg_if fix for slow Wishbone slaves |
julius |
4919d 05h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 546 |
ORPSoC update: Fix WB B3 bursting termination on error in WB B3 RAM model |
julius |
4919d 22h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 545 |
ORPSoC - revert unecessary i2c fix - driver oneliner was all that was needed. |
julius |
4926d 00h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 543 |
i2c_master_slave bug fix for slave, potentially holding SDA low when master wants to send stop. |
julius |
4926d 07h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 537 |
ORPSoC or1200 fix for l.rfe bug, and when multiply is disabled. |
julius |
4942d 18h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 536 |
ORPSoC - removing duplicate ethmac toplevel file. |
julius |
4946d 08h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 530 |
ORPSoC update
Ethernet MAC Wishbone interface fixes
Beginnings of software update.
ML501 backend script fixes for new ISE |
julius |
4955d 07h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 506 |
ORPSoC or1200 interrupt and syscall generation test |
julius |
4981d 01h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 505 |
OR1200 overflow detection fixup
SPIflash program update
or1200 driver library timer improvement |
julius |
4981d 02h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 504 |
ORPSoC ALU update with new comparison configuration option, software test for comparisons and register file comment cleanup |
julius |
4997d 22h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 503 |
ORPSoC's or1200 defines fix to indicate we don't actually have I/DMMU invalidate registers. |
julius |
4998d 18h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 502 |
ORPSoC update - or1200, ethmac Xilinx fifos
or1200 in ORPSoC has carry bit, overflow bit, and range exception added and tested. New software tests in ORPSoC library. Ml501 build had ethmac fifos added, and or1200_defines updated to use these new or1200 features by default |
julius |
5000d 22h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 501 |
ORPSoC or1200 mult/mac/divide unit serial arith bug fixed.
ORPSoC or1200 defines now use serial divide by default |
julius |
5001d 22h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 499 |
ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup |
julius |
5002d 18h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 485 |
ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 |
julius |
5036d 07h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 479 |
ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. |
julius |
5054d 11h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 478 |
ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups. |
julius |
5056d 02h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 477 |
ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each. |
julius |
5056d 11h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 476 |
ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more. |
julius |
5057d 04h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
