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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] - Rev 794

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794 ORPSoC, or1200: split out or1200_fpu_intfloat_conv_except module into own file

Fixes lint warnings.
julius 4437d 04h /openrisc/trunk/orpsocv2/rtl/verilog/
788 or1200: Patch from R Diez to remove l.cust5 signal from a sensitivty list when it's not defined.

Signed-off-by: R Diez <rdiezmail-openrisc@yahoo.de>
Acked-by: Julius Baxter <juliusbaxter@gmail.com>
julius 4461d 18h /openrisc/trunk/orpsocv2/rtl/verilog/
679 Allow setting the boot address as an external
parameter. If no parameter is used, the value
from OR1200_BOOT_ADR will be used

Signed-off-by: Olof Kindgren <olof@opencores.org>
Acked-by: Julius Baxter <juliusbaxter@gmail.com>
olof 4485d 18h /openrisc/trunk/orpsocv2/rtl/verilog/
672 ORPSoC: Fix Bug 76 - Incorrect unsigned integer less-than compare with COMP3 option enabled

OR1200 RTL fix and software test added.
julius 4564d 14h /openrisc/trunk/orpsocv2/rtl/verilog/
655 ORPSoC: add CFI flash controller to ml501, sw driver, tests, app, documentation julius 4615d 16h /openrisc/trunk/orpsocv2/rtl/verilog/
619 ORPSoC OR1200 fix and regression test for bug 51.

signed-off Julius Baxter
reviewed by Stefan Kristiansson
julius 4696d 15h /openrisc/trunk/orpsocv2/rtl/verilog/
618 Remove unused parameter Tp olof 4696d 23h /openrisc/trunk/orpsocv2/rtl/verilog/
570 Fix white space in ethmac headers olof 4711d 18h /openrisc/trunk/orpsocv2/rtl/verilog/
547 ORPSoC dbg_if fix for slow Wishbone slaves julius 4759d 01h /openrisc/trunk/orpsocv2/rtl/verilog/
546 ORPSoC update: Fix WB B3 bursting termination on error in WB B3 RAM model julius 4759d 18h /openrisc/trunk/orpsocv2/rtl/verilog/
545 ORPSoC - revert unecessary i2c fix - driver oneliner was all that was needed. julius 4765d 20h /openrisc/trunk/orpsocv2/rtl/verilog/
543 i2c_master_slave bug fix for slave, potentially holding SDA low when master wants to send stop. julius 4766d 03h /openrisc/trunk/orpsocv2/rtl/verilog/
537 ORPSoC or1200 fix for l.rfe bug, and when multiply is disabled. julius 4782d 15h /openrisc/trunk/orpsocv2/rtl/verilog/
536 ORPSoC - removing duplicate ethmac toplevel file. julius 4786d 04h /openrisc/trunk/orpsocv2/rtl/verilog/
530 ORPSoC update

Ethernet MAC Wishbone interface fixes

Beginnings of software update.

ML501 backend script fixes for new ISE
julius 4795d 03h /openrisc/trunk/orpsocv2/rtl/verilog/
506 ORPSoC or1200 interrupt and syscall generation test julius 4820d 21h /openrisc/trunk/orpsocv2/rtl/verilog/
505 OR1200 overflow detection fixup

SPIflash program update

or1200 driver library timer improvement
julius 4820d 22h /openrisc/trunk/orpsocv2/rtl/verilog/
504 ORPSoC ALU update with new comparison configuration option, software test for comparisons and register file comment cleanup julius 4837d 18h /openrisc/trunk/orpsocv2/rtl/verilog/
503 ORPSoC's or1200 defines fix to indicate we don't actually have I/DMMU invalidate registers. julius 4838d 14h /openrisc/trunk/orpsocv2/rtl/verilog/
502 ORPSoC update - or1200, ethmac Xilinx fifos
or1200 in ORPSoC has carry bit, overflow bit, and range exception added and tested. New software tests in ORPSoC library. Ml501 build had ethmac fifos added, and or1200_defines updated to use these new or1200 features by default
julius 4840d 18h /openrisc/trunk/orpsocv2/rtl/verilog/

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