URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] - Rev 55

Rev	Log message	Author	Age	Path
55	Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk	julius	5362d 00h	/openrisc/trunk/orpsocv2/rtl/verilog/
54	wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist	julius	5372d 07h	/openrisc/trunk/orpsocv2/rtl/verilog/
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5405d 06h	/openrisc/trunk/orpsocv2/rtl/verilog/
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5424d 00h	/openrisc/trunk/orpsocv2/rtl/verilog/
46	debug interfaces now support byte and non-aligned accesses from gdb	julius	5439d 11h	/openrisc/trunk/orpsocv2/rtl/verilog/
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5475d 10h	/openrisc/trunk/orpsocv2/rtl/verilog/
43	Couple of fixes to ORPSoC, new linux patch version in toolchain script	julius	5499d 07h	/openrisc/trunk/orpsocv2/rtl/verilog/
41	Update to or1k top	julius	5518d 06h	/openrisc/trunk/orpsocv2/rtl/verilog/
6	Checking in ORPSoCv2	julius	5537d 23h	/openrisc/trunk/orpsocv2/rtl/verilog/