| Rev |
Log message |
Author |
Age |
Path |
| 69 |
ORPSoC xilinx ml501 board update - added ethernet eupport and software test |
julius |
5285d 18h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 67 |
New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory |
julius |
5288d 13h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 65 |
ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix |
julius |
5312d 17h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 63 |
Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. |
julius |
5325d 09h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 58 |
ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up |
julius |
5367d 05h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 57 |
ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words |
julius |
5372d 09h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 55 |
Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk |
julius |
5383d 01h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 54 |
wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist |
julius |
5393d 09h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 51 |
ORPSoCv2 updates: cycle accurate profiling, ELF loading |
julius |
5426d 08h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 49 |
Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update |
julius |
5445d 01h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 46 |
debug interfaces now support byte and non-aligned accesses from gdb |
julius |
5460d 13h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 44 |
New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades |
julius |
5496d 12h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 43 |
Couple of fixes to ORPSoC, new linux patch version in toolchain script |
julius |
5520d 09h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 41 |
Update to or1k top |
julius |
5539d 07h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 6 |
Checking in ORPSoCv2 |
julius |
5559d 00h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
