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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [clkgen/] - Rev 780

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Rev Log message Author Age Path
363 ORPSoC's RTL code fixed to pass linting by Verilator.

ORPSoC's debug interface disabled for now in both RTL and System C top level.

Profiled building of cycle-accurate model now done correctly.
julius 5181d 06h /openrisc/trunk/orpsocv2/rtl/verilog/clkgen/
362 ORPSoCv2 verilator building working again. Board build fixes to follow julius 5182d 15h /openrisc/trunk/orpsocv2/rtl/verilog/clkgen/
361 OPRSoCv2 - adding things left out in last check-in julius 5182d 19h /openrisc/trunk/orpsocv2/rtl/verilog/clkgen/

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