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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [ethmac/] - Rev 502

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Rev Log message Author Age Path
502 ORPSoC update - or1200, ethmac Xilinx fifos
or1200 in ORPSoC has carry bit, overflow bit, and range exception added and tested. New software tests in ORPSoC library. Ml501 build had ethmac fifos added, and or1200_defines updated to use these new or1200 features by default		 julius 4986d 05h /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/
485 ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 julius 5021d 14h /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.		 julius 5081d 08h /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/
409 ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it.
Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build.
Updated documentation.		 julius 5114d 10h /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/
408 ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too. julius 5114d 23h /openrisc/trunk/orpsocv2/rtl/verilog/eth/
403 ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. julius 5116d 04h /openrisc/trunk/orpsocv2/rtl/verilog/eth/
360 First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken julius 5168d 06h /openrisc/trunk/orpsocv2/rtl/verilog/eth/
69 ORPSoC xilinx ml501 board update - added ethernet eupport and software test julius 5371d 20h /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/
55 Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk julius 5469d 03h /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/
6 Checking in ORPSoCv2 julius 5645d 02h /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/

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