| Rev |
Log message |
Author |
Age |
Path |
| 679 |
Allow setting the boot address as an external
parameter. If no parameter is used, the value
from OR1200_BOOT_ADR will be used
Signed-off-by: Olof Kindgren <olof@opencores.org>
Acked-by: Julius Baxter <juliusbaxter@gmail.com> |
olof |
4517d 18h |
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/ |
| 672 |
ORPSoC: Fix Bug 76 - Incorrect unsigned integer less-than compare with COMP3 option enabled
OR1200 RTL fix and software test added. |
julius |
4596d 14h |
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/ |
| 619 |
ORPSoC OR1200 fix and regression test for bug 51.
signed-off Julius Baxter
reviewed by Stefan Kristiansson |
julius |
4728d 15h |
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/ |
| 537 |
ORPSoC or1200 fix for l.rfe bug, and when multiply is disabled. |
julius |
4814d 14h |
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/ |
| 505 |
OR1200 overflow detection fixup
SPIflash program update
or1200 driver library timer improvement |
julius |
4852d 21h |
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/ |
| 504 |
ORPSoC ALU update with new comparison configuration option, software test for comparisons and register file comment cleanup |
julius |
4869d 17h |
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/ |
| 502 |
ORPSoC update - or1200, ethmac Xilinx fifos
or1200 in ORPSoC has carry bit, overflow bit, and range exception added and tested. New software tests in ORPSoC library. Ml501 build had ethmac fifos added, and or1200_defines updated to use these new or1200 features by default |
julius |
4872d 17h |
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/ |
| 501 |
ORPSoC or1200 mult/mac/divide unit serial arith bug fixed.
ORPSoC or1200 defines now use serial divide by default |
julius |
4873d 18h |
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/ |
| 499 |
ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup |
julius |
4874d 14h |
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/ |
| 485 |
ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 |
julius |
4908d 03h |
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/ |
| 479 |
ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. |
julius |
4926d 06h |
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/ |
| 478 |
ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups. |
julius |
4927d 22h |
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/ |
| 477 |
ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each. |
julius |
4928d 06h |
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/ |
| 476 |
ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more. |
julius |
4928d 23h |
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/ |
| 462 |
ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.
RAM models updated. |
julius |
4936d 05h |
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/ |
| 456 |
ORPSoCv2 or1200 - SPRs module format and comment update. Or1200 monitor Verilog now displays report and exit l.nops to stdout by default. |
julius |
4947d 22h |
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/ |
| 435 |
ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality. |
julius |
4974d 12h |
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/ |
| 426 |
ORPSoC update
Reverted back to previous OR1200 instruction cache.
(...which...)
Fixed or1200-except test failure on generic model.
ML501 build not passing or1200-except test. Tried disabling
burst on the bus (memory server doesn't support it yet) to
no avail. To be continued... |
julius |
4987d 11h |
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/ |
| 415 |
ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash. |
julius |
4995d 21h |
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/ |
| 412 |
ORPSoC update - Rearranged Xilinx ML501, simulations working again. |
julius |
4999d 11h |
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/ |
