OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [orpsoc_top/] - Rev 761

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
506 ORPSoC or1200 interrupt and syscall generation test julius 4981d 06h /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/
485 ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 julius 5036d 12h /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.
julius 5096d 06h /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/
415 ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash.
julius 5124d 07h /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/
403 ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. julius 5131d 02h /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/
363 ORPSoC's RTL code fixed to pass linting by Verilator.

ORPSoC's debug interface disabled for now in both RTL and System C top level.

Profiled building of cycle-accurate model now done correctly.
julius 5181d 13h /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/
360 First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken julius 5183d 04h /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.