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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [ram_wb/] - Rev 507

Rev	Log message	Author	Age	Path
462	ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim. RAM models updated.	julius	4922d 11h	/openrisc/trunk/orpsocv2/rtl/verilog/ram_wb/
439	ORPSoC update Ethernet MAC synthesis issues with Actel Synplify D-2009.12A Ethernet MAC FIFO synthesis issues with Xilinx XST Multiply/divide tests for to run on target. Added third interface to ram_wb module, changed reference design RAM to ram_wb wrapper. Updated verilog and system C monitor modules accordingly. Added ability to use ram_wb as internal memory on ML501 design. Fixed ethernet MAC tests for ML501.	julius	4954d 02h	/openrisc/trunk/orpsocv2/rtl/verilog/ram_wb/
412	ORPSoC update - Rearranged Xilinx ML501, simulations working again.	julius	4985d 16h	/openrisc/trunk/orpsocv2/rtl/verilog/ram_wb/
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5041d 00h	/openrisc/trunk/orpsocv2/rtl/verilog/ram_wb/
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5385d 03h	/openrisc/trunk/orpsocv2/rtl/verilog/components/ram_wb/
6	Checking in ORPSoCv2	julius	5517d 20h	/openrisc/trunk/orpsocv2/rtl/verilog/components/ram_wb/