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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [smii/] - Rev 370

Rev	Log message	Author	Age	Path
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5037d 19h	/openrisc/trunk/orpsocv2/rtl/verilog/smii/
55	Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk	julius	5338d 16h	/openrisc/trunk/orpsocv2/rtl/verilog/components/smii/
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5400d 16h	/openrisc/trunk/orpsocv2/rtl/verilog/components/smii/
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5452d 03h	/openrisc/trunk/orpsocv2/rtl/verilog/components/smii/
6	Checking in ORPSoCv2	julius	5514d 15h	/openrisc/trunk/orpsocv2/rtl/verilog/components/smii/