URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [uart16550/] - Rev 619

Rev	Log message	Author	Age	Path
364	OR1200 passes verilator lint. Mainly fixes to widths, and all case statements altered to casez and Xs changed to ?s. OR1200 PIC default width back to 31 (was accidentally changed to ORPSoC's 20 last checkin) OR1200 spec updated to version 0.9, various updates. OR1200 in ORPSoC and main OR1200 in sync, only difference is defines.	julius	5177d 03h	/openrisc/trunk/orpsocv2/rtl/verilog/uart16550/
363	ORPSoC's RTL code fixed to pass linting by Verilator. ORPSoC's debug interface disabled for now in both RTL and System C top level. Profiled building of cycle-accurate model now done correctly.	julius	5177d 13h	/openrisc/trunk/orpsocv2/rtl/verilog/uart16550/
361	OPRSoCv2 - adding things left out in last check-in	julius	5179d 02h	/openrisc/trunk/orpsocv2/rtl/verilog/uart16550/
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5179d 03h	/openrisc/trunk/orpsocv2/rtl/verilog/uart16550/
55	Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk	julius	5480d 00h	/openrisc/trunk/orpsocv2/rtl/verilog/components/uart16550/
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5593d 11h	/openrisc/trunk/orpsocv2/rtl/verilog/components/uart16550/
6	Checking in ORPSoCv2	julius	5655d 23h	/openrisc/trunk/orpsocv2/rtl/verilog/components/uart16550/