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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [wb_ram_b3/] - Rev 435

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Rev	Log message	Author	Age	Path
363	ORPSoC's RTL code fixed to pass linting by Verilator. ORPSoC's debug interface disabled for now in both RTL and System C top level. Profiled building of cycle-accurate model now done correctly.	julius	5177d 13h	/openrisc/trunk/orpsocv2/rtl/verilog/wb_ram_b3/
362	ORPSoCv2 verilator building working again. Board build fixes to follow	julius	5178d 22h	/openrisc/trunk/orpsocv2/rtl/verilog/wb_ram_b3/
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5179d 03h	/openrisc/trunk/orpsocv2/rtl/verilog/wb_ram_b3/
353	OR1200 RTL and ORPSoCv2 update, fixing Verilator build capability. * or1200/rtl/verilog/or1200_sprs.v: Verilator public and access comments * orpsocv2/rtl/verilog/components/or1200/or1200_sprs.v: "" * or1200/rtl/verilog/or1200_ctrl.v: Verilator public and access comments * orpsocv2/rtl/verilog/components/or1200/or1200_ctrl.v: "" * or1200/rtl/verilog/or1200_except.v: Verilator public and access comments * orpsocv2/rtl/verilog/components/or1200/or1200_except.v: "" * orpsocv2/rtl/verilog/components/wb_ram_b3/wb_ram_b3.v: Some Verilator related Lint issues fixed. ORPSoCv2: Removed bus arbiter snooping functions from OrpsocAccess and updated RAM model hooks for new RAM. * orpsocv2/bench/sysc/include/Or1200MonitorSC.h: Remove arbiter snooping * orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp: "" * orpsocv2/bench/sysc/include/OrpsocAccess.h: Remove arbiter snooping, change include and classes for new RAM model. * orpsocv2/bench/sysc/src/OrpsocAccess.cpp: "" or_debug_proxy - fixing sleep and Windows make issues: * or_debug_proxy/src/gdb.c: Removed all sleep - still to be fixed properly * or_debug_proxy/Makefile: Remove VPI file when building on Cygwin (deprecated) ORPmon play around, various changes to low level files.	julius	5181d 05h	/openrisc/trunk/orpsocv2/rtl/verilog/components/wb_ram_b3/
351	OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO	julius	5182d 03h	/openrisc/trunk/orpsocv2/rtl/verilog/components/wb_ram_b3/

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