| Rev |
Log message |
Author |
Age |
Path |
| 411 |
Improved ethmac testbench and software.
Renamed some OR1200 library functions to be more generic.
Fixed bug with versatile_mem_ctrl for Actel board.
Added ability to simulate gatelevel modules alongside RTL modules
in board build. |
julius |
4949d 17h |
/openrisc/trunk/orpsocv2/sim/ |
| 403 |
ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. |
julius |
4952d 11h |
/openrisc/trunk/orpsocv2/sim/ |
| 397 |
ORPSoCv2:
doc/ path added, with Texinfo documentation. Still a work in progress.
VPI files updated.
OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.
Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build. |
julius |
4954d 17h |
/openrisc/trunk/orpsocv2/sim/ |
| 393 |
ORPSoCv2 software rearrangement in progress. Basic tests should now run again. |
julius |
4957d 16h |
/openrisc/trunk/orpsocv2/sim/ |
| 363 |
ORPSoC's RTL code fixed to pass linting by Verilator.
ORPSoC's debug interface disabled for now in both RTL and System C top level.
Profiled building of cycle-accurate model now done correctly. |
julius |
5002d 23h |
/openrisc/trunk/orpsocv2/sim/ |
| 362 |
ORPSoCv2 verilator building working again. Board build fixes to follow |
julius |
5004d 08h |
/openrisc/trunk/orpsocv2/sim/ |
| 360 |
First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken |
julius |
5004d 13h |
/openrisc/trunk/orpsocv2/sim/ |
| 356 |
Added new simple MAC test to ORPSoC test suite:
* orpsocv2/sw/or1200asm/or1200asm-mac.S: Added
Fixed MAC pipeline issue in OR1200
* or1200/rtl/verilog/or1200_mult_mac.v: Made mac_op valid only once per insn.
* orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v: ""
* orpsocv2/sw/dhry/dhry.c: Changed final output to be same as ORPmon version
* orpsocv2/sim/bin/Makefile: Added new MAC test to default tests |
julius |
5005d 07h |
/openrisc/trunk/orpsocv2/sim/ |
| 354 |
Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut
* sw/support/crt0.S: Tick timer interrupt to increment variable
now in place instead of calling customisable
interrupt vector handler
Changed all system frequencies in design to 50MHz. |
julius |
5006d 13h |
/openrisc/trunk/orpsocv2/sim/ |
| 351 |
OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO |
julius |
5007d 13h |
/openrisc/trunk/orpsocv2/sim/ |
| 348 |
First stage of ORPSoCv2 update - more to come |
julius |
5007d 17h |
/openrisc/trunk/orpsocv2/sim/ |
| 78 |
Fixed typo in Silos workaround script |
rherveille |
5160d 12h |
/openrisc/trunk/orpsocv2/sim/ |
| 77 |
Added support for Silvaco's Silos simulator
Added workaround for Silos's exit code behaviour |
rherveille |
5160d 12h |
/openrisc/trunk/orpsocv2/sim/ |
| 76 |
Added: +libext+.v
Added: +incdir+. |
rherveille |
5161d 12h |
/openrisc/trunk/orpsocv2/sim/ |
| 70 |
ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\! |
julius |
5208d 02h |
/openrisc/trunk/orpsocv2/sim/ |
| 69 |
ORPSoC xilinx ml501 board update - added ethernet eupport and software test |
julius |
5208d 03h |
/openrisc/trunk/orpsocv2/sim/ |
| 68 |
Fixed up a couple of Makefile things in ORPSoCv2 |
julius |
5210d 19h |
/openrisc/trunk/orpsocv2/sim/ |
| 67 |
New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory |
julius |
5210d 22h |
/openrisc/trunk/orpsocv2/sim/ |
| 66 |
Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. |
julius |
5230d 20h |
/openrisc/trunk/orpsocv2/sim/ |
| 64 |
Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. |
julius |
5237d 21h |
/openrisc/trunk/orpsocv2/sim/ |
