URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sim/] - Rev 53

Rev	Log message	Author	Age	Path
53	Fixed incorrect commandline option for ORPSoC and main makefile setting	julius	5346d 15h	/openrisc/trunk/orpsocv2/sim/
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5361d 13h	/openrisc/trunk/orpsocv2/sim/
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5380d 07h	/openrisc/trunk/orpsocv2/sim/
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5431d 18h	/openrisc/trunk/orpsocv2/sim/
43	Couple of fixes to ORPSoC, new linux patch version in toolchain script	julius	5455d 15h	/openrisc/trunk/orpsocv2/sim/
42	Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model	julius	5471d 12h	/openrisc/trunk/orpsocv2/sim/
40	Added GDB server to verilog simulation via VPI and make target to build and run this model	julius	5475d 18h	/openrisc/trunk/orpsocv2/sim/
36	Better clean rule in makefile	julius	5489d 19h	/openrisc/trunk/orpsocv2/sim/
6	Checking in ORPSoCv2	julius	5494d 06h	/openrisc/trunk/orpsocv2/sim/