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[/] [openrisc/] [trunk/] [orpsocv2/] [sim/] - Rev 61

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Rev Log message Author Age Path
58 ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up julius 5325d 06h /openrisc/trunk/orpsocv2/sim/
57 ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words julius 5330d 10h /openrisc/trunk/orpsocv2/sim/
55 Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk julius 5341d 02h /openrisc/trunk/orpsocv2/sim/
54 wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist julius 5351d 10h /openrisc/trunk/orpsocv2/sim/
53 Fixed incorrect commandline option for ORPSoC and main makefile setting julius 5369d 10h /openrisc/trunk/orpsocv2/sim/
51 ORPSoCv2 updates: cycle accurate profiling, ELF loading julius 5384d 09h /openrisc/trunk/orpsocv2/sim/
49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 5403d 02h /openrisc/trunk/orpsocv2/sim/
44 New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades julius 5454d 13h /openrisc/trunk/orpsocv2/sim/
43 Couple of fixes to ORPSoC, new linux patch version in toolchain script julius 5478d 10h /openrisc/trunk/orpsocv2/sim/
42 Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model julius 5494d 07h /openrisc/trunk/orpsocv2/sim/
40 Added GDB server to verilog simulation via VPI and make target to build and run this model julius 5498d 14h /openrisc/trunk/orpsocv2/sim/
36 Better clean rule in makefile julius 5512d 14h /openrisc/trunk/orpsocv2/sim/
6 Checking in ORPSoCv2 julius 5517d 01h /openrisc/trunk/orpsocv2/sim/

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